![]() ![]() +-++++- Select 8 KiB PRG bank at $8000 or $C000 depending on Swap Mode the 8 KiB page at $C000 is controlled by the $800x register.the 8 KiB page at $8000 is fixed to the second last 8 KiB in the ROM.the 8 KiB page at $C000 is fixed to the second last 8 KiB in the ROM.the 8 KiB page at $8000 is controlled by the $800x register.the 8 KiB page at $6000 is WRAM, and WRAM content can be read and written.the 8 KiB page at $6000 is open bus, and WRAM content cannot be read nor written.PRG Swap Mode/WRAM control ($9002) VRC4 7 bit 0 ![]() This page lists registers as they are in the VRC2b and VRC4f variants (iNES mapper 23). CPU $E000-$FFFF: 8 KiB PRG ROM bank, fixed to the last bank.CPU $C000-$DFFF (or $8000-$9FFF): 8 KiB PRG ROM bank, fixed to the second-last bank.CPU $8000-$9FFF (or $C000-$DFFF): 8 KiB switchable PRG ROM bank.CPU $6000-$7FFF: optional 8 KiB PRG RAM bank.CPU $6000-$6FFF: optional 2 KiB PRG RAM bank (mirrored once), or.CPU $C000-$FFFF: 16 KiB PRG ROM bank, fixed to the last 16 KiB.CPU $A000-$BFFF: 8 KiB switchable PRG ROM bank.CPU $8000-$9FFF: 8 KiB switchable PRG ROM bank.PPU $1C00-$1FFF: 1 KiB switchable CHR bank.PPU $1800-$1BFF: 1 KiB switchable CHR bank.PPU $1400-$17FF: 1 KiB switchable CHR bank.PPU $1000-$13FF: 1 KiB switchable CHR bank.PPU $0C00-$0FFF: 1 KiB switchable CHR bank.PPU $0800-$0BFF: 1 KiB switchable CHR bank.PPU $0400-$07FF: 1 KiB switchable CHR bank.PPU $0000-$03FF: 1 KiB switchable CHR bank.With an NES 2.0 header, a submapper may be used to specify which address mapping to use, and either VRC2 or VRC4. Additionally, the VRC4 is always presumed for these three mappers. INES mappers 21, 23 and 25 each implements two address mappings at the same time:īecause the address pairings do not overlap, and the games appear to use these registers in a well behaved manner, it is presumed sufficient for compatibility in most cases. For the one game with 8 KiB of RAM, an external circuit was added. The RAM decoding circuit that's part of the VRC4 itself only decodes RAM from $6000-$6FFF. The VRC2a (mapper 22) additionally wires the CHR banking lines differently (see below). Horizontal, vertical and 1-screen mirroring.In particular, two lines chosen from A0-A7 will be used to select registers. The primary difference between them was having the mapper address lines connected in different ways. The VRC2 and VRC4 were used with several similar but incompatible boards. This section describes how each variation presents itself to the NES CPU considering the different PCBs. Considering the mapper chip itself, all VRC2 behave the same way and all VRC4 behave the same way. Variations VRC2a/b/c and VRC4a/b/c/d/e/f are referring to different PCB layouts. 3.1 PRG Swap Mode/WRAM control ($9002) VRC4. ![]()
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